State machines built from integrated circuits need to be radioactively hardened to prevent soft errors that occur when a high energy particle travels through the integrated circuit's semiconductor substrate. This is particularly important when the state machine is to operate in high radiation environments such as outer space. An ionizing particle traveling through the semiconductor substrate may cause a transient voltage glitch, i.e., a single event transient (SET), or may cause a sequential state element to store the wrong state, i.e., a single event upset (SEU).
One technique for preventing the effects of high energy radiation is to provide a self-correcting triple-redundant (TR) circuit. In this manner, if a radiation strike results in a soft error in one copy of the circuit, the other two copies of the circuit can correct the soft error in the affected copy of the circuit through self-correction techniques. However, charge collection can affect multiple circuit nodes, requiring the critical nodes of redundant circuits to be spatially separated so that one ionizing track does not affect multiple circuit nodes, thereby defeating the self-correcting mechanism of the redundancy.
Triple-mode redundancy (TMR) has been used extensively in many state machines, such as Field Programmable Gate Arrays (FPGAs). Unfortunately, the arrangement and functionality of these circuits has proven inadequate in high radiation environments. In particular, these FPGAs suffer from “domain crossing” errors where charge collection can affect multiple circuit copies, thwarting TMR correction. It is thus essential that a logic design methodology aimed at application specific integrated circuits (ASICs) guarantee an adequate minimum spatial separation of critical nodes, which is difficult since standard CAD software, whether aimed at FPGAs or ASICs, attempts to minimize delay and power by placing logic nodes as close to each other as possible.
Accordingly, what is needed are more robust radiation hardened integrated circuit configurations and techniques to design radiation hardened integrated circuits.